Hi Dr Teo,
I am confuse regarding the tag in cache and virtual memory paging and would to clarify
Direct Memory Access (DMA)
Dear Dr. Jason,
Based on my understanding about cycle stealing mode during the lecture, after the DMA taking control of the data bus, CPU goes on with its internal work.
Polled I/O and Interrupt
1) Why Polled I/O use less hardware interface circuitry between I/O device and processor then Interrupt I/O?
I2C
I2C is a very robust protocol. The designers choose to include the start/stop sequence, probably to make the communication more robust. I2C is synchronous, not asynchronous.
Flash, floating gate
This is with regards to the two techniques used to program and erase FLASH memory in the memory lecture. There were discrepancies between the content discussed in the lecture notes and further readings I’ve done on the topic.
Parity and baud rate
- if there is a even number of ‘1’s and parity used is even, so the parity bit will be 0? [Jason] Yes.
Serial, full-duplex, data transfer
in the quiz question 1, it asked how many physical connection is needed.
Cycle period, Tutorial #5 Q4
I am confuse over the conversion of cycle per second and the cycle period with bytes during the tutorial class and hope that you can provide some guidance on this kind of question.
Why blog?
CE/CZ1006 is an important module that every computer science and computer engineering student must take at the freshman year. The curriculum is rigorous and hands-on. With a cohort of 360 students in AY2013-2014 Semester 2, I am very happy (but not surprised) to receive many emails. Many asked for clarifications on lecture slides, tutorials and labs. Others ask ‘advanced’ questions beyond the scope of the syllabus. This blog collates the questions and answers. Hopefully, this will help other students with similar doubts. Happy learning and good luck with the examinations!