Dear Dr. Jason,

Based on my understanding about cycle stealing mode during the lecture, after the DMA taking control of the data bus, CPU goes on with its internal work.

It means DMA is using the time interval when CPU don’t need the data bus.

[Jason] Ideally so.

And if the DMA needs a longer time than the interval, CPU will ‘wait’ for DMA to complete and then take back the control of data bus.

I hope my understanding so far is correct.

[Jason] Yes.

So the cycle stealing mode needs a time LONGER than CPU’s original time(because of the ‘waiting time’, which there is not such a case in transparent mode),

AND the time should be shorter than (individual CPU work time + block data transferring time), (because part of DMA’s work is done when CPU don’t need the data bus, they are working concurrently)

I hope so far it is correct.

[Jason] Transparent mode may be considered a subset of cycle-stealing where the DMA time (setup+transfer+release) is equal to or less than the CPU period, so it is “transparent”. When DMA access the bus, CPU does not, please remember that. In Transparent mode, DMA use the CPU cycles that do not need system bus access.

And in the tutorial question I am confused,

Like question 7) and 8), it seems to directly add up the (CPU cycle time) and (DMA transmitting time),

I suppose there are some “overlapping” intervals should be deducted, and where is it?

[Jason] Please talk to me after the lecture to clarify on this point. Hard to address over email.

Question 6) is not covered during the lecture, and I also have some difficulty understanding some concepts in the answer, is it required?

[Jason] It is inevitable, as you have not covered cache and virtual memory fully. This question is not significant, but the concepts are worthy.

Question 7) mentioned that “Assume the processor is running on a 1MHz clock and each DMA transfer requires 1 cycle”, but it is not used for the calculation, what does it indicate, especially the “each DMA transfer requires 1 cycle”?

Best regards,

Tang Cheng