This is a good question. Thanks for bringing it up. Prof Goh briefly mentioned about Pipelined Processor in one slide (Chapter 6 slide 9).

In Week #12 on the topic of “Parallelism”, we will discuss about pipelining in more details. In all our discussions, we are assuming non-pipelined processor. DMA transfer is more complicated for pipelined processors. There are more DMA features that we have not discussed (for instance, DMA with interrupt-trigger, multi-channel DMA).

In a non-pipelined processor, an instruction may take one or more clock cycles to execute. This provides the opportunity to use particular clock cycle(s) for cycle stealing. I’ll consider transparent mode as a subset of cycle stealing where the time taken (dma setup + data transfer + dma release) is less than or equal to the cycle period. In tutorial #5 Q7, you are told the instruction takes one clock cycle. For ease of calculation, we assume cycle stealing occurs at the end of every instruction, and use the provided information to calculate the effective time period for each instruction cycle with DMA cycle stealing, and determined the perceived “slow-down”.

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Dear Prof. Teo Kian Jin Jason,

I am a student of CE1006. I have a question about the transparent mode of DMA.

In the lecture notes, it says that the DMA controller only take control of the system bus when the CPU is not using it, aka, during the decoding and execution period. But in the first half of this semester, we learnt about pipelining, which means while decoding, the CPU is also fetching the next instruction. It’s basically the same for execution as well. So, because of pipelining, the CPU is always using the system bus, leaving no chance for the DMA controller to access the system bus in the transparent mode. Is this true?

Best Regards

SUN Ximeng (Nathaniel)