If you refer to “Computer Arithmetic Part 2” slides 9, 10 and 11, you will see Add’.
Cache Memory
When the CPU needs a data (from main memory), it’ll provide the memory address for that data.
Polled I/O and VIP ALU
Hardware Multiplier and Booth Algorithm
Hi Tang Cheng,
Please refer to my comments below.
DMA mode in pipelined processor?
This is a good question. Thanks for bringing it up. Prof Goh briefly mentioned about Pipelined Processor in one slide (Chapter 6 slide 9).
Empty cache: Hit or miss?
Computer Interface & Magnetic Hard-disk
Dear Prof Teo
Do you mind explaining tutorial 5.2 question 3f
Bus cycle
In the question, I believe the CPU takes one clock cycle to access the system bus. Hence, the bus cycle refers to the CPU clock cycle.
Polled I/O and Interrupt-trigger I/O
Dear Delconi,
Please refer to my comment below.
Carry flag
Dear Du Qiu,
This is a good question, but let me correct your initial question.